| 1. | Processors implementing the instruction queue prefetch algorithm are rather technically advanced.
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| 2. | The instruction queues dispatch up to eight instructions to the execution units.
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| 3. | Decoded instructions are queued in instruction queues and are issued when their operands are available.
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| 4. | Each of the instruction queues can accept up to four instructions from the decoder, avoiding any bottlenecks.
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| 5. | After the introduction of prefetch instruction queue in the 8086 processor, all successive processors have incorporated this feature.
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| 6. | The instruction queues issue their instructions to their execution units dynamically depending on the availability of operands and resources.
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| 7. | During the second stage, four instructions were taken from the instruction buffer, decoded, and issued to instruction queues.
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| 8. | In stage three, instructions in the instruction queues that are ready for execution have their operands read from the register files.
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| 9. | Due to the instruction cache's two cycle latency and the instruction queues, the average branch misprediction penalty is 11 cycles.
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| 10. | The instruction pipeline has an instruction queue that can fetch 6 instructions per cycle; and issue up to 10 instructions per cycle.
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